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CY7C1359A/GVT71256T18
256K x 18 Synchronous-Pipelined Cache Tag RAM
Features
* * * * * * * * * * * * * * * * * * * Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V -5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs JTAG boundary scan Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low-profile JEDEC standard 100-pin TQFP package All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), Global Write (GW), and Data Input Enable (DEN). Asynchronous inputs include the Burst Mode Control (MODE), the Output Enable (OE) and the Match Output Enable (MOE). The data outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Data inputs are registered with Data Input Enable (DEN) and chip enable pins (CE, CE2, and CE2). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1-DQ9. WEH controls DQ10-DQ18. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The CY7C1359C/GVT71256T18 operates from a +3.3V power supply with output power supply being +2.5V or +3.3V. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 8 MB secondary cache.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.
Selection Guide
7C1359A-166 71256T36-6 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 3.5 310 20 7C1359A-150 71256T36-6.7 3.8 275 20 7C1359A-133 71256T36-7.5 4.0 250 20 7C1359A-100 71256T36-10 4.5 190 20
Cypress Semiconductor Corporation Document #: 38-05120 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 13, 2001
CY7C1359A/GVT71256T18
Functional Block Diagram--256Kx18[1]
HIGHER BYTE WRITE
WEH# BWE#
D
Q
D
LOWER BYTE WRITE
Q
WEL# GW# CE# CE2 CE2# ZZ OE# ADSP# MOE# Power Down Logic Latch
D
Q
lo byte write hi byte write
ENABLE
D
Q
D
Q
D
Q
MATCH
Compare
DEN# Latch CLK A ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic 16 Address Register
Input Register
OUTPUT REGISTER
256K x 9 x 2 SRAM Array
Output Buffers
D
Q
DQ1DQ18
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
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CY7C1359A/GVT71256T18
Pin Configurations
100-Pin TQFP Top View
A A CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A NC NC NC VCCQ VSSQ NC NC DQ10 DQ11 VSSQ VCCQ DQ12 DQ13 NC VCC NC VSS DQ14 DQ15 VCCQ VSSQ DQ16 DQ17 DQ18 NC VSSQ VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1359A/GVT71256T18
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSSQ NC DQ9 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ MATCH DEN MOE
1 A B C D E F G H J K L M N P R T U Document #: 38-05120 Rev. ** VCCQ NC NC DQ10 NC VCCQ NC DQ13 VCCQ NC DQ15 VCCQ DQ17 NC NC NC VCCQ
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
119-Lead BGA Top View 2 A CE2 A NC DQ11 NC DQ12 NC VCC DQ14 NC DQ16 NC DQ18 A A TMS 3 A A A VSS VSS VSS WEH VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS WEL VSS VSS VSS NC A TDO 6 A CE2 A DQ9 NC DQ7 NC DQ5 VCC NC DQ3 MATCH DQ2 MOE A A NC 7 VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ DEN DQ1 NC ZZ VCCQ Page 3 of 24
CY7C1359A/GVT71256T18
Pin Descriptions
BGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 5L 3G TQFP Pins 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 93 94 Name A0 A1 A Type InputSynchronous Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle.
WEL WEH
InputSynchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. WEL controls DQ1-DQ9. WEH controls DQ10-DQ18. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control, and data input enable control input on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active LOW input is used to enable the device. Chip Enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
4M
87
BWE
InputSynchronous InputSynchronous
4H
88
GW
4K
89
CLK
InputSynchronous
4E 6B 2B 4F 4G
98 92 97 86 83
CE CE2 CE2 OE ADV
InputSynchronous InputSynchronous inputSynchronous Input InputSynchronous InputSynchronous InputSynchronous
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
InputStatic
7T
64
ZZ
InputSnooze: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). InputSynchronous Output Data Input Enable: This active LOW input is used to control the update of data input registers. Match Output: MATCH will be HIGH if data in the data input registers match the data stored in the memory array, assuming MOE being LOW. MATCH will be LOW if data do not match.
7N 6M
52 53
DEN MATCH
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CY7C1359A/GVT71256T18
Pin Descriptions (continued)
BGA Pins 6P 7P, 6N, 6L, 7K, 6H, 7G, 6F, 7E, 6D, 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 5U 2U 3U 4U 4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U TQFP Pins 51 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 42 38 39 43 15, 41,65, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 Name MOE DQ1- DQ18 Type Input Input/ Output Description Match Output Enable: This active LOW asynchronous input enables the MATCH output drivers. Data Inputs/Outputs: Input data must meet setup and hold times around the rising edge of CLK.
TDO TMS TDI TCK VCC VSS
Output Input
IEEE 1149.1 test output. LVTTL-level output. IEEE 1149.1 test inputs. LVTTL-level inputs.
Supply Ground
Power Supply: +3.3V -5% and +10% Ground: GND
4, 11, 20, 27, 54, 61, 70, 77
VCCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to VCC)
1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16, 2D, 4D, 7D, 1E, 25, 28-30, 56, 57, 6E, 2F, 1G, 6G, 66, 75, 78, 79, 95, 2H, 7H, 3J, 5J, 96 1K, 6K, 2L, 4L, 7L, 2N, 1P, 1R, 5R, 7R, 1T, 4T, 6U
NC
-
No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
Burst Address Table (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
Partial Truth Table for MATCH[2, 3, 4, 5, 6]
Operation READ Cycle WRITE Cycle Fill WRITE Cycle COMPARE Cycle Deselected Cycle (MATCH Out) Deselected Cycle E L L L L H H WE H L L H X X DEN X L H L X X MOE X X X L L H OE L H H H X X MATCH Output H High-Z DQ Q D High-Z D High-Z High-Z
Notes: 2. X means "don't care." H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW. 3. E=L is defined as CE=LOW and CE2=LOW and CE2=HIGH. E =H is defined as CE=HIGH or CE2=HIGH or CE2=LOW. WE is defined as [BWE + WEL*WEH]*GW. 4. All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
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CY7C1359A/GVT71256T18
Truth Table[5, 6, 7, 8, 9, 10, 11]
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L L L X X H H X H X X H H X H CE2 CE2 ADSP X X H X H L L L L L X X X X X X X X X X X X X L X L X H H H H H X X X X X X X X X X X X X L L H H L L H H H H H X X H X H H X X H X ADSC L X X L L X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X L H H H H H H L L H H H H L L OE X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Partial Truth Table for READ/WRITE[12]
Function READ READ WRITE one byte WRITE all bytes WRITE all bytes GW H H H H L BWE H L L L X WEH X H L L X WEL X H H L X
Notes: 7. X means "Don't Care." H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW. 8. WEL enables write to DQ1-DQ9. WEH enables write to DQ10-DQ18. 9. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 10. Suspending burst generates wait cycle. 11. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. 12. X means "don't care." H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW.
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CY7C1359A/GVT71256T18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAP's operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. Performing a TAP Reset The TAP circuitry does not have a Reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state.
Test Access Port (TAP) Registers
Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAP's registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for a x36 device and 51 bits for a x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/ PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit's position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number.
Test Access Port (TAP)
TCK - Test Clock (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS - Test Mode Select (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. TDI - Test Data In (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 2.) TDO - Test Data Out (OUTPUT) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.)
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CY7C1359A/GVT71256T18
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device's input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use.
TAP Controller Instruction Set
Overview There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in
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CY7C1359A/GVT71256T18
1
TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0
0
REUN-TEST/ IDLE
1
SELECT DR-SCAN 0 1
1
Figure 1. TAP Controller State Diagram[13]
Note: 13. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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CY7C1359A/GVT71256T18
0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO
2 Instruction Register
1
0
31 30
29
.
.
2
1
0
Identification Register
x
.
.
.
.
2
1
0
Boundary Scan Register [14]
TDI TAP Controller TDI
Figure 2. TAP Controller Block Diagram
TAP DC Electrical Characteristics (20C < Tj < 110C; VCC = 3.3V -0.2V and +0.3V unless otherwise noted)
Parameter VIH VIl ILI ILO VOLC VOHC VOLT VOHT Description Input High (Logic 1) Voltage[15, 16] Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current LVCMOS Output Low Voltage[15, 17] LVCMOS Output High Voltage LVTTL Output Low Voltage[15] LVTTL Output High Voltage
[15] [15, 17] [15, 16]
Test Conditions
Min. 2.0 -0.3
Max. VCC + 0.3 0.8 5.0 5.0 0.2
Unit V V A A V V V V
0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100 A IOHC = 100 A IOLT = 8.0 mA IOHT = 8.0 mA
-5.0 -5.0
VCC - 0.2 0.4 2.4
Notes: 14. X = 53 for this device. 15. All Voltage referenced to VSS (GND). 16. Overshoot: VIH(AC)Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
TAP AC Switching Characteristics Over the Operating Range[18, 19]
Parameter Clock tTHTH fTF tTHTL tTLTH Output Times tTLQX tTLQV tDVTH tTHDX Set-up Times tMVTH tCS Hold Times tTHMX tCH TMS Hold Capture Hold 5 5 ns ns TMS Set-up Capture Set-up 5 5 ns ns TCK LOW to TDO Unknown TCK LOW to TDO Valid TDI Valid to TCK HIGH TCK HIGH to TDI Invalid 5 5 0 10 ns ns ns ns Clock Cycle Time Clock Frequency Clock HIGH Time Clock LOW Time 8 8 20 50 ns MHz ns ns Description Min. Max Unit
Notes: 18. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 19. Test conditions are specified using the load in TAP AC Test Conditions.
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CY7C1359A/GVT71256T18
TAP Timing and Test Conditions
TDO Z0 = 50 50 Vt = 1.5V Figure 5 (a) TAP AC OUTPUT LOAD EQUIVALENT
tTHTH t
ALL INPUT PULSES 3.0V
20 pF
VSS 1.0 ns
1.5V 1.0 ns
THTL
t
TLTH
TEST CLOCK (TCK)
tMVTH tTHMX
TEST MODE SELECT (TMS)
tDVTH t
THDX
TEST DATA IN (TDI)
t
TLQV
tTLQX
TEST DATA OUT (TDO)
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CY7C1359A/GVT71256T18
Identification Register Definitions
Instruction Field REVISION NUMBER (31:28) DEVICE DEPTH (27:23) DEVICE WIDTH (22:18) RESERVED (17:12) CYPRESS JEDEC ID CODE (11:1) ID Register Presence Indicator (0) 512K x 18 XXXX 00111 00011 XXXXXX 00011100100 1 Description Reserved for revision number. Defines depth of 256K words. Defines width of x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. Indicates the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 54
Instruction Codes
Instruction EXTEST Code 000 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant. Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction does not affect device operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. Do not use these instructions; they are reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not affect device operations. This instruction does not implement IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Places the bypass register between TDI and TDO. This instruction does not affect device operations.
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Boundary Scan Order
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name A A A A A A A MOE DEN MATCH DQ1 DQ2 DQ3 DQ4 ZZ DQ5 DQ6 DQ7 DQ8 DQ9 A A A ADV ADSP ADSC OE BWE GW CLK CE2 WEL WEH CE2 TQFP 44 45 46 47 48 49 50 51 52 53 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86 87 88 89 92 93 94 97 Bump ID 2R 2T 3T 5T 6R 3B 5B 6P 7N 6M 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H 4K 6B 5L 3G 2B Range Com'l (Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ..........-0.5V to +4.6V VIN .......................................................... -0.5V to VCC+0.5V Storage Temperature (plastic) ................... -55C to +150C Junction Temperature ............................................... +150C Power Dissipation.......................................................... 1.0W Short Circuit Output Current........................................ 50 mA
Boundary Scan Order (continued)
Bit# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Signal Name CE A A DQ10 DQ11 DQ12 DQ13 NC DQ14 DQ15 DQ16 DQ17 DQ18 MODE A A A A A1 A0 TQFP 98 99 100 8 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37 Bump ID 4E 3A 2A ID 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
Maximum Ratings
Operating Range
Ambient Temperature[20] 0C to +70C VCC 3.3V -5%/+10%
Note: 20. TA is the case temperature.
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Electrical Characteristics Over the Operating Range
Parameter VIHD VIH VIl ILI ILO VOH VOH VOL VCC VCCQ Output Low Voltage Supply Voltage
[15] [15, 23]
Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current
[22] [15, 21]
Test Conditions Data Inputs (DQxx) All Other Inputs
[15, 21]
Min. 1.7 1.7 -0.3 -2 -2 2.4 1.7
Max. VCC+0.3 4.6 0.8 2 2
Unit V V V A A V
0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0 mA at VCCQ = 3.135V IOH = -4.0 mA at VCCQ = 2.375V IOL = 8.0 mA
Output Leakage Current Output High Voltage[15, 23]
0.4 3.135 2.375 3.6 VCC 133 MHz/ -7.5 250 100 MHz/ -10 190
V V V
I/O Supply Voltage[15]
Parameter ICC
Description Power Supply Current: Operating[24, 25, 26]
Conditions Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open
Typ. 100
166 MHz/ -6 310
150 MHz/ -6.7 275
Unit mA
ISB2
CMOS Standby[25, 26] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC - 0.2; all inputs static; CLK frequency = 0 TTL Standby[25, 26] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min.
5
10
10
10
10
mA
ISB3
10
20
20
20
20
mA
ISB4
Clock Running[25, 26]
40
80
70
60
50
mA
Capacitance[17]
Parameter CI CO Description Input Capacitance Input/Output Capacitance (DQ) Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Typ. 4 7 Max. 5 8 Unit pF pF
Thermal Resistance
Description Test Conditions Symbol BGA Typ. TQFP Typ. JA JC 19 9 25 9 Unit C/W C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer PCB Thermal Resistance (Junction to Case)
Note: 21. Overshoot: VIH +6.0V for t tKC /2. Undershoot:VIL -2.0V for t tKC /2. 22. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of 30 A. 23. AC I/O curves are available upon request. 24. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 25. "Device Deselected" means the device is in Power-Down mode as defined in the truth table. "Device Selected" means the device is active. 26. Typical values are measured at 3.3V, 25C, and 8.5-ns cycle time.
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
AC Test Loads and Waveforms
DQ Z0 = 50 50 Vt = 1.25V 30 pF
DQ 1,538 5 pF +2.5v
ALL INPUT PULSES 2.5V 10% 0V 90% 90% 10%
1,667
1.8 ns
1.8 ns
(a)
(b) (b)
(c)
Switching Characteristics Over the Operating Range[27]
-6 166 MHz Parameter Clock tKC tKF tKH tKL tKQ tKM tKQX tKMX tKQLZ tKQHZ tOEQ tMOEM tOELZ tMOELZ tOEHZ tMOEHZ Set-up Times tS Hold Times tH Address, Controls, and Data In[31] 0.5 0.5 0.5 0.5 ns
Notes: 27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted. 28. Output loading is specified with CL = 5 pF as in AC Test Loads. 29. At any given temperature and voltage condition, tKQHZ is less than tKQLZ, tOEHZ is less than tOELZ and tMOEHZ is less than tMOELZ. 30. OE is a "Don't Care" after a write cycle begins To prevent bus contention, OE should be negated prior before the start of write cycle. 31. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for "don't care" as defined in the truth table.
-6.7 150 MHz Min. 6.7 2.6 2.6 Max.
-7.5 133 MHz Min. 7.5 2.8 2.8 Max.
-10 100 MHz Min. 8.5 3.4 3.4 Max. Unit ns ns ns 4.0 1.5 0 ns ns ns 8.5 3.8 0 ns ns ns 3.8 ns
Description
Clock Cycle Time Clock Frequency Clock HIGH Time Clock LOW Time
Min. 6.0 2.4 2.4
Max.
Output Times Clock to Output Valid Clock to MATCH Valid Clock to Output Invalid Clock to MATCH Invalid Clock to Output in Low-Z[17, 28, 29] Clock to Output in High-Z OE to Output Valid
[30] [17, 28, 29]
3.5 1.5 0 1.5 6.0 3.5 0 3.5 0 1.5 0 1.5
3.8 1.5 0 6.7 3.5 0 3.5 1.5
4.0
7.5 3.8
1.5
MOE to MATCH Valid[30] OE to Output in Low-Z[17, 28, 29] MOE to MATCH in Low-Z
[17, 28, 29]
OE to Output in High-Z[17, 28, 29] MOE to MATCH in High-Z[17, 28, 29] Address, Controls, and Data In[31] 1.5
3.8
1.5
1.5
2.0
ns
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Typical Output Buffer Characteristics
Output High Voltage VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4 Pull-Up Current IOH (mA) Min. -38 -38 -38 -26 -20 0 0 0 0 IOH (mA) Max. -105 -105 -105 -83 -70 -30 -10 0 0 Output Low Voltage VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 Pull-Down Current IOL (mA) Min. IOL(mA) Max. 0 0 10 20 31 40 40 40 40 0 0 20 40 63 80 80 80 80
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Switching Waveforms
Read Timing with Burst Feature[32, 33]
tKC tKL
CLK
tS tKH
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE#, GW# CE#
A1
tH
A2
tS
tS
ADV#
tH
OE#
tKQ tKQLZ tOELZ
Q(A1)
tOEQ
tKQ
Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)
DQ
SINGLE READ
BURST READ
Notes: 32. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active. 33. In this timing diagram, it is assumed that DEN is tied to LOW (VSS).
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Write Timing with Burst Feature[32, 33]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE# GW#
A1
tH
A2
A3
CE#
tS
ADV#
tH
OE#
tKQX tOEHZ
D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
DQ
Q
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Read/Write Timing with Burst Feature[32, 33]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE#, GW# CE#
A1
A2
tH
A3
A4
A5
ADV#
OE#
DQ
Q(A1) Single Reads
Q(A2)
D(A3) Single Write
Q(A4)
Q(A4+1) Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Document #: 38-05120 Rev. **
Page 20 of 24
CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Read/Write Timing without Burst Feature[32, 34, 35]
tKH tKC tKL
CLK
tS
ADDRESS
A1
A2
tH
A3
A4
A5
A6
A7
A8
WE#
CE#
DEN#
tOEQ tOEHZ tKQHZ tOELZ tKQLZ
Q(A1) Q(A2)
OE#
tKQ
Q(A3)
tKQX
Q(A4) D(A5) D(A6) D(A7) D(A8)
DQ
Reads
Writes
Notes: 34. In this timing diagram, it is assumed that burst feature is not used and therefore ADSP is tied to HIGH (VCC) and ADSC is tied to LOW (VSS). The logic state of ADV is a "Don't Care". 35. In this timing diagram, it is assumed that WE = [BWE + WEL*WEH]*GW.
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Compare/Fill Write Timing[32, 34, 35]
tKH tKC tKL
CLK
tS
ADDRESS
A1
tH
A1
A2
WE#
CE#
DEN#
OE#
DQ
D(A1)
D(A2)
MOE#
tMOELZ
tKM
tMOEHZ
tMOEM
MATCH HIGH CHIP DESELECTED
MATCH
tKMX
MISS
FILL WRITE
HIT
Document #: 38-05120 Rev. **
Page 22 of 24
CY7C1359A/GVT71256T18
Ordering Information
Speed (MHz) 166 150 133 100 Ordering Code CY7C1359A-166AC/ GVT71256T18T-6 CY7C1359A-150AC/ GVT71256T18T-6.7 CY7C1359A-133AC/ GVT71256T18T-7.5 CY7C1359A-100AC/ GVT71256T18T-10 Package Name A101 A101 A101 A101 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1359A/GVT71256T18
Document Title: CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM Document Number: 38-05120 REV. ** ECN NO. 108311 Issue Date 09/25/01 Orig. of Change BRI Description of Change New Cypress spec--converted from Galvantech format
Document #: 38-05120 Rev. **
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